Many systems exist wherein a reference signal having a predetermined frequency is sampled or reconstructed after being transmitted. Such reference signals often have information associated with the reference signal frequency. In order to recover the information from the signal, it is necessary to reestablish the frequency and phase of the reference signal. Environments in which such signals may appear include communications systems, computer disk drive systems, and video systems. In video imaging systems, a particular frequency is used to transmit data, such as pixel (picture element) information for producing a digital image of an analog video signal. Certainly other applications also exist.
The preferred embodiment of the present invention is directed to video digitizers wherein an analog video signal, constituting a displayed raster image, is quantitized and subsequently reduced to a hard-copy rendition by a printer.
The video signal is composed of a stream of discrete and generally differing analog values corresponding to viewable pixels and non-viewable image justification elements required to construct an image frame on a CRT display. The image frame is output by the display system at a periodic rate in "row/column" format. Timing and synchronization information required to delineate line and frame boundaries may be embedded in the video signal or conveyed through separate signal paths. A plurality of video signals are generally required to support color images.
The video digitizer may capture the display image through oversampling at greater than the Nyquist rate with attendant image processing and memory size and/or bandwidth penalties, or through synchronous sampling where each pixel of the analog video signal is sampled once per primary color. The latter topology requires a phase coherent digitizing signal, but offers significant advantages in reducing cost and complexity of implementation, which advantages accrue directly from the present invention.
Synchronous sampling in a video environment dictates that the display system pixel clock be available for generation of the digitization signal. As the pixel clock is generally not available outside the display system it must be reconstructed from the timing/synchronization signals output to the CRT display. The timing/synchronization signals are H Sync and V Sync representing display line and frame delimiters respectively.
Conventionally, pixel clock recovery is accomplished through phase locked loop frequency synthesis using H Sync as the PLL reference. The PLL multiplies the input frequency, H Sync, by the value placed in the feedback scaler of the PLL. Specifying a value equal to the display system's total number of pixels per display line (viewable & non-viewable) results in a PLL clock output frequency equal to the display system pixel clock frequency. Assuming an ideal PLL implementation, zero phase error will be observed between the PLL reference signal (H Sync) and the PLL feedback ("carry" output from the feedback scaler) and clock output signals. The recovered pixel clock (PLL clock) may then be used through selectively gating to form the digitization signal to an analog to digital convertor for the purpose of quantitizing the analog video signal on a per pixel basis.
The digitization signal is synchronous and phase coherent to the analog video signal, it however may not exhibit the optimum phase relationship for sampling of video due to differential delays within the display system, cable delays, less than ideal PLL implementations, etc. Furthermore, the video signal may exhibit amplitude aberrations in the form of ringing, due to bandwidth limitations, and/or due to the introduction of synchronous artifacts from the display system controller.
Conventionally, sampling phase adjustment is provided by routing the digitization signal through a multiplicity of lumped constant LC delay lines with the delay nodes available at the inputs of digital signal data selectors. The output of the data selector is then made available to the analog to digital convertor conveying a time delayed replica of the original digitization signal. The desired delay is specified via channel select control inputs to the data selector. Disadvantages of this methodology include the minimum delays achievable being greater than the time resolution required, volumetric and power inefficiencies and expense of the delay lines and data selectors, and delay increments being dimensioned in time rather than in percentages of a pixel.